 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ECLTSSOP20EVB Evaluation Board Manual for High Frequency TSSOP 20 http://onsemi.com EVALUATION BOARD MANUAL INTRODUCTION ON Semiconductor has developed an evaluation board for the devices in 20-lead TSSOP package. These evaluation boards are offered as a convenience for the customers interested in performing their own engineering assessment on the general performance of the 20-lead TSSOP device samples. The board provides a high bandwidth 50 W controlled impedance environment. Figures 1 and 2 show the top and bottom view of the evaluation board, which can be configured in several different ways, depending on device under test (see Table 1. Configuration List). This evaluation board manual contains: This manual should be used in conjunction with the device data sheet, which contains full technical details on the device specifications and operation. Board Lay-Up * * * * Information on 20-lead TSSOP Evaluation Board Assembly Instructions Appropriate Lab Setup Bill of Materials The 20-lead TSSOP evaluation board is implemented in four layers with split (dual) power supplies (see Figure 3. Evaluation Board Lay-Up). For standard ECL lab setup and test, a split (dual) power supply is essential to enable the 50 W internal impedance in the oscilloscope as a termination for ECL devices. The first layer or primary trace layer is 0.008 thick Rogers RO4003 material, which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz copper ground. The FR4 dielectric material is placed between second and third layer and between third and fourth layer. The third layer is the power plane (VCC & VEE) and a portion of this layer is a ground plane. The fourth layer is the secondary trace layer. Figure 1. Top View of the 20-lead TSSOP Evaluation Board (c) Semiconductor Components Industries, LLC, 2003 1 May, 2003 - Rev. 1 Publication Order Number: ECLTSSOP20EVB/D ECLTSSOP20EVB Bottom View Expanded Bottom View Figure 2. Bottom View of the 20-lead TSSOP Evaluation Board LAY-UP DETAIL 4 LAYER SILKSCREEN (TOP SIDE) LAYER 1 (TOP SIDE) 1 OZ ROGERS 4003 0.008 in LAYER 2 (GROUND PLANE P1) 1 OZ FR-4 0.020 in LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ FR-4 0.025 in LAYER 4 (BOTTOM SIDE) 1 OZ 0.062 $ 0.007 Figure 3. Evaluation Board Lay-up Board Layout The 20-lead TSSOP evaluation board was designed to be versatile and accommodate several different configurations. The input, output, and power pin layout of the evaluation board is shown in Figures 4 and 5. The evaluation board has at least eight possible configurable options. Table 1, list the devices and the relevant configuration that utilizes this PCB board. Lists of components and simple schematics are located in Figures 6 through 12. Place SMA connectors on J1 through J20, 50 W chip resistors between ground pad and Pin 1 pad through Pin 20 pad, and chip capacitors C1 through C5 according to configuration figures. (C4 and C5 are 0.01 mF and C1, C2, and C3 are 0.1 mF); (See Figure 5). http://onsemi.com 2 ECLTSSOP20EVB Top View Bottom View Figure 4. Evaluation Board Layout http://onsemi.com 3 ECLTSSOP20EVB VEE VCC Pin 20 Pin 19 Pin 18 Pin 17 Pin 16 Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 C5 C4 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Ground Figure 5. Enlarged Bottom View of the Evaluation Board Table 1. Configuration List Configuration 1 2 3 4 5 6 7 Comments See Figure 6 See Figure 7 See Figure 8 See Figure 9 See Figure 10 See Figure 11 See Figure 12 Device EP14, LVEP14 EP17, LVEP17 EP29 EP40 EP56, LVEP56 EP57 EP139 http://onsemi.com 4 ECLTSSOP20EVB Evaluation Board Assembly Instructions The 20-lead TSSOP evaluation board is designed for characterizing devices in a 50 W laboratory environment using high bandwidth equipment. Each signal trace on the board has a via, which has an option of placing a termination resistor depending on the input/output configuration (see Table 1, Configuration List). Table 11 contains the Bill of Materials for this evaluation board. Solder the Device on the Evaluation Board It is recommended to solder 0.01 mF capacitors to C4 and C5 to reduce the unwanted noise from the power supplies. C1, C2, and C3 pads are provided for 0.1 mF capacitor to further diminish the noise from the power supplies. Adding capacitors can improve edge rates, reduce overshoot and undershoot. Termination The soldering can be accomplished by hand soldering or soldering re-flow techniques. Make sure pin 1 of the device is located next to the white dotted mark and all the pins are aligned to the footprint pads. Solder the 20-lead TSSOP device to the evaluation board. Connecting Power and Ground Planes For standard ECL lab setup and test, a split (dual) power supply is required enabling the 50 W internal impedance in the oscilloscope to be used as a termination of the ECL signals (VTT = VCC - 2.0 V, in split power supply setup, VTT is the system ground, VCC is 2.0 V, and VEE is -3.0 V or -1.3 V; see Table 2, Power Supply Levels). Table 2. Power Supply Levels Power Supply 5.0 V 3.3 V 2.5 V VCC 2.0 V 2.0 V 2.0 V VEE -3.0 V -1.3 V -0.5 V GND 0.0 V 0.0 V 0.0 V All ECL outputs need to be terminated to VTT (VTT = VCC -2.0 V = GND) via a 50 W resistor. 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver (More information on termination is provided in AN8020). Solder the chip resistors to the bottom side of the board between the appropriate input of the device pin pads and the ground pads. For ease of assembly, it is advised to place and solder termination resistors on its vertical (side) position, instead of its original or flat position. Installing the SMA Connectors Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given configuration. Each input and output requires one SMA connector. Attach all the required SMA connectors onto the board and solder the connectors to the board on J1 through J20. Please note that alignment of the signal connector pin of the SMA can influence the lab results. The reflection and launch of the signals are largely influenced by imperfect alignment and soldering of the SMA connector. Validating the Assembled Board Connect three banana jack sockets to VCC, VEE, and GND labeled holes. Wire bond the appropriate device pin pad on the bottom side of the board to VCC and VEE power stripes. (Device specific, please see configuration for each desired device. See Figure 5) After assembling the evaluation board, it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process. Time Domain Reflectometry (TDR) is another highly recommended validation test. http://onsemi.com 5 ECLTSSOP20EVB CONFIGURATIONS SMA CONNECTORS J1 J2 J3 J4 J5 BANANA JACK PLUG 0603 CHIP CAPACITOR 0.1 mF J19 J17 J16 J6 J7 J8 J9 J10 J12 J13 J14 NORMAL TOP VIEW EP14 / LVEP14 0603 CHIP CAPACITOR 0.01 mF VEE VCC PIN 1 WIRE 0402 CHIP RESISTOR 50 W 0805 CHIP CAPACITOR 0.01 mF EXPANDED BOTTOM VIEW EP14 / LVEP14 Figure 6. Configuration 1 Table 3. Configuration 1 (Device EP14 and LVEP14) Device Pin # Connector Resistor Power J1 1 Yes No No J2 2 Yes No No J3 3 Yes No No J4 4 Yes No No J5 5 Yes No No J6 6 Yes No No J7 7 Yes No No J8 8 Yes No No J9 9 Yes No No J10 10 Yes No No J11 11 No No VEE J12 12 Yes Yes No J13 13 Yes Yes No J14 14 Yes Yes No J15 15 Yes No No J16 16 Yes Yes No J17 17 Yes Yes No J18 18 No No VCC J19 19 Yes Yes No J20 20 No No VCC http://onsemi.com 6 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 mF J2 J3 J4 J5 BANANA JACK PLUG J19 J18 J17 J16 J6 J7 J8 J9 J12 J13 J15 J14 NORMAL TOP VIEW EP17 / LVEP17 0603 CHIP CAPACITOR 0.01 mF VEE VCC PIN 1 WIRE 0402 CHIP RESISTOR 50 W 0805 CHIP CAPACITOR 0.01 mF EXPANDED BOTTOM VIEW EP17 / LVEP17 Figure 7. Configuration 2 Table 4. Configuration 2 (Device EP17 and LVEP17) Device Pin # Connector Resistor Power J1 1 No No VCC J2 2 Yes Yes No J3 3 Yes Yes No J4 4 Yes Yes No J5 5 Yes Yes No J6 6 Yes Yes No J7 7 Yes Yes No J8 8 Yes Yes No J9 9 Yes Yes No J10 10 Yes No No J11 11 No No VEE J12 12 Yes No No J13 13 Yes No No J14 14 Yes No No J15 15 Yes No No J16 16 Yes No No J17 17 Yes No No J18 18 Yes No No J19 19 Yes No No J20 20 No No VCC http://onsemi.com 7 ECLTSSOP20EVB SMA CONNECTORS J1 J2 J3 J4 J5 BANANA JACK PLUG 0603 CHIP CAPACITOR 0.1 mF J19 J18 J17 J16 J6 J7 J8 J9 J12 J13 J15 J14 NORMAL TOP VIEW EP29 0603 CHIP CAPACITOR 0.01 mF VEE VCC PIN 1 WIRE 0402 CHIP RESISTOR 50 W 0805 CHIP CAPACITOR 0.01 mF EXPANDED BOTTOM VIEW EP29 Figure 8. Configuration 3 Table 5. Configuration 3 (Device EP29) Device Pin # Connector Resistor Power J1 1 Yes Yes No J2 2 Yes No No J3 3 Yes Yes No J4 4 Yes Yes No J5 5 Yes Yes No J6 6 Yes Yes No J7 7 Yes Yes No J8 8 Yes Yes No J9 9 Yes Yes No J10 10 No No VCC J11 11 No No VEE J12 12 Yes Yes No J13 13 Yes Yes No J14 14 Yes No No J15 15 Yes No No J16 16 Yes No No J17 17 Yes No No J18 18 Yes Yes No J19 19 Yes Yes No J20 20 No No VCC http://onsemi.com 8 ECLTSSOP20EVB SMA CONNECTORS J2 J3 J4 J5 BANANA JACK PLUG 0603 CHIP CAPACITOR 0.1 mF J19 J17 J16 J6 J7 J8 J9 J10 J15 J14 0603 CHIP CAPACITOR 0.01 mF VEE VCC PIN 1 NORMAL TOP VIEW EP40 0603 CHIP CAPACITOR 0.01 mF VEE VCC PIN 1 WIRE WIRE 0402 CHIP RESISTOR 50 W 0805 CHIP CAPACITOR EXPANDED BOTTOM VIEW EP40 0.01 mF (Option 1 Internal Termination Resistor) 0805 CHIP CAPACITOR EXPANDED BOTTOM VIEW EP40 0.01 mF (Option 2 External Termination Resistor) Figure 9. Configuration 4 Table 6. Configuration 4 (Device EP40) (Options 1 & 2) Device Pin # J1 1 J2 2 J3 3 J4 4 J5 5 J6 6 J7 7 J8 8 J9 9 J10 10 J11 11 J12 12 J13 13 J14 14 J15 15 J16 16 J17 17 J18 18 J19 19 J20 20 Option 1 Internal Termination Resistor Configuration Connector Resistor Power No No VEE Yes No Gnd Yes No Gnd Yes No No Yes No No Yes No No Yes No No Yes No Gnd Yes No Gnd Yes No No No No VEE No No No No No VCC Yes No No Yes No No Yes No No Yes No No No No VCC Yes No No No No VCC Option 2 External Termination Resistor Configuration Connector Resistor Power No No VEE Yes No No Yes No No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes No No Yes No No Yes No No No No VEE No No No No No VCC Yes No No Yes No No Yes No No Yes No No No No VCC Yes No No No No VCC http://onsemi.com 9 ECLTSSOP20EVB SMA CONNECTORS J1 J2 0603 CHIP CAPACITOR 0.1 mF J19 J18 J17 J4 J5 BANANA JACK PLUG J16 J6 J7 J13 J9 J10 J12 J15 NORMAL TOP VIEW EP56 / LVEP56 PIN 1 VEE VCC 0603 CHIP CAPACITOR 0.01 mF WIRE 0402 CHIP RESISTOR 50 W 0805 CHIP CAPACITOR 0.01 mF EXPANDED BOTTOM VIEW EP56 / LVEP56 Figure 10. Configuration 5 Table 7. Configuration 5 (Device EP56 and LVEP56) Device Pin # Connector Resistor Power J1 1 Yes Yes No J2 2 Yes Yes No J3 3 Yes No No J4 4 Yes Yes No J5 5 Yes Yes No J6 6 Yes Yes No J7 7 Yes Yes No J8 8 Yes No No J9 9 Yes Yes No J10 10 Yes Yes No J11 11 No No VEE J12 12 Yes No No J13 13 Yes No No J14 14 No No VCC J15 15 Yes Yes No J16 16 Yes Yes No J17 17 Yes Yes No J18 18 Yes No No J19 19 Yes No No J20 20 No No VCC http://onsemi.com 10 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 mF J2 J3 J4 J5 BANANA JACK PLUG J19 J18 J16 J6 J7 J8 J9 J12 J13 J15 NORMAL TOP VIEW EP57 VEE VCC 0603 CHIP CAPACITOR 0.01 mF PIN 1 WIRE 0402 CHIP RESISTOR 50 W 0805 CHIP CAPACITOR 0.01 mF EXPANDED BOTTOM VIEW EP57 Figure 11. Configuration 6 Table 8. Configuration 6 (Device EP57) Device Pin # Connector Resistor Power J1 1 No No VCC J2 2 Yes Yes No J3 3 Yes Yes No J4 4 Yes Yes No J5 5 Yes Yes No J6 6 Yes Yes No J7 7 Yes Yes No J8 8 Yes Yes No J9 9 Yes Yes No J10 10 No No VEE J11 11 No No VEE J12 12 Yes No No J13 13 Yes No No J14 14 No No VCC J15 15 Yes No No J16 16 Yes No No J17 17 No No VCC J18 18 Yes Yes No J19 19 Yes Yes No J20 20 No No VCC http://onsemi.com 11 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 mF J2 J3 J4 J5 BANANA JACK PLUG J19 J18 J17 J16 J6 J7 J13 J9 J10 J12 J15 J14 NORMAL TOP VIEW EP139 0603 CHIP CAPACITOR 0.01 mF WIRE VEE VCC PIN 1 0402 CHIP RESISTOR 50 W 0805 CHIP CAPACITOR 0.01 mF EXPANDED BOTTOM VIEW EP139 Figure 12. Configuration 7 Table 9. Configuration 7 (Device EP139) Device Pin # Connector Resistor Power J1 1 No No VCC J2 2 Yes Yes No J3 3 Yes Yes No J4 4 Yes Yes No J5 5 Yes Yes No J6 6 Yes No No J7 7 Yes Yes No J8 8 No No VCC J9 9 Yes Yes No J10 10 Yes Yes No J11 11 No No VEE J12 12 Yes No No J13 13 Yes No No J14 14 Yes No No J15 15 Yes No No J16 16 Yes No No J17 17 Yes No No J18 18 Yes No No J19 19 Yes No No J20 20 No No VCC http://onsemi.com 12 ECLTSSOP20EVB LAB SETUP Power Supply VCC GND VEE Test Measuring Equipment Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Trigger J2 J3 J4 J5 J6 J7 J8 D U T J13 J12 Out1 Out1 J1 Differential Signal Generator Trigger Figure 13. Example of Standard Lab Setup (Configuration 1) 1. Connect appropriate power supplies to VCC, VEE, and GND. For standard ECL lab setup and test, a split (dual) power supply is required enabling the 50 W internal impedance in the oscilloscope to be used as a termination of the ECL signals (VTT = VCC - 2.0 V, in split power supply setup, VTT is the system ground, VCC is 2.0 V, and VEE is -3.0 V or -1.3 V; see Table 10). 2. Connect a signal generator to the input SMA connectors. Setup input signal according to the device data sheet. 3. Connect a test measurement device on the device output SMA connectors. NOTE: The test measurement device must contain 50 W termination. Table 10. Power Supply Levels Power Supply 5.0 V 3.3 V 2.5 V VCC 2.0 V 2.0 V 2.0 V VEE -3.0 V -1.3 V -0.5 V GND 0.0 V 0.0 V 0.0 V http://onsemi.com 13 ECLTSSOP20EVB Table 11. Bill of Materials Components SMA Connector Banana Jack Manufacturer Johnson Components* Keystone* Description SMA Connector, Side Launch, Gold Plated Standard Jack Miniature Jack Chip Capacitor Johanson Dielectric* 0603 0.01 mF 0805 0.01 mF 0603 0.1 mF Chip Resistor Evaluation Board Device Samples Panasonic* ON Semiconductor ON Semiconductor 0402 50 W 1% Precision Think Film Chip Resistor TSSOP 20 Evaluation Board TSSOP 20 Package Device Part Number 142-0701-851 6096 6090 500R14Z100MV4E 500R15Z100MV4E 250R14Z101MV4E ERJ-2RKF49R9X ECLTSSOP20EVB Various http://www.panasonic.com http://www.onsemi.com http://www.onsemi.com http://www.johansondielectrics.com Web Site http://www.johnsoncomponents.com http://www.keyelco.com *Components are available through most distributors, i.e. www.newark.com, www.digikey.com. http://onsemi.com 14 ECLTSSOP20EVB Top View Second Layer (Ground Plane) Figure 14. Gerber Files http://onsemi.com 15 ECLTSSOP20EVB Third Layer (Power and Ground Plane) (Left side - VCC, Right side - VEE, Middle Box - Ground) Bottom Layer Figure 15. Gerber Files http://onsemi.com 16 ECLTSSOP20EVB Notes http://onsemi.com 17 ECLTSSOP20EVB ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 18 ECLTSSOP20EVB/D |
Price & Availability of ECLTSSOP20EVB
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |